![modelsim 10 commands modelsim 10 commands](https://www.nandland.com/vhdl/tutorials/images/tutorial-modelsim-beginner-8.png)
The other annoying problem I can think of is that it becomes difficult to find out programmatically if the simulation was successful. That’s because the assert statement is supposed to indicate an error condition and not the successful completion of the simulation. It says that it’s a “failure”, but the test is “OK” at the same time. Just make sure to use severity level failure, as shown in the example below.Īssert false report "Test: OK" severity failure Īnd why do I hate this way of stopping a successful simulation?įirst of all, it’s looks strange and confusing to see the printout from the above example: No additional imports are needed, and it works in all VHDL versions. That was the first way someone taught me to end the simulation when I was learning VHDL at the university. It takes an integer status value, but the behavior varies among simulators.Ī failsafe and universal way to stop a VHDL testbench is to create an assertion failure. As shown below, an overloaded version of the procedure exists. Just like the finish procedure, stop requires VHDL-2008 or newer. # Stopped at ~/stop_tb/src/using_stop_tb.vhd line 23
![modelsim 10 commands modelsim 10 commands](https://images2017.cnblogs.com/blog/650701/201708/650701-20170802152534161-272958340.jpg)
# Break in Process SEQUENCER_PROC at ~/stop_tb/src/using_stop_tb.vhd line 23 # Time: 1 ms Iteration: 0 Instance: /using_stop_tb To get out of the Tcl shell, we would have to type vsim -c -do 'vsim ing_stop_tb run -all' After the simulation stops, we are still in ModelSim.
![modelsim 10 commands modelsim 10 commands](http://www.pldworld.com/_hdl/2/_ref/se_html/tutorial_html/images/coverage_summary.gif)
The listing below shows the output from running the testbench that uses the stop procedure in batch mode. Instead of returning control to the caller, ModelSim opens a Tcl command shell, causing the calling script to hang indefinitely.
MODELSIM 10 COMMANDS HOW TO
The example below shows how to import and use the stop procedure.Ī problem with using stop in script-based setups is that it doesn’t quit the simulation.
MODELSIM 10 COMMANDS SIMULATOR
The simulator treats it like a breakpoint. That may be useful if you want to examine signal values manually or even continue the simulation later. The VHDL stop procedure causes the simulation to pause.
MODELSIM 10 COMMANDS CODE
However, you can control the Linux exit code value in ModelSim by using the Tcl command exit -code, but that’s another story. The wording in the VHDL-2008 standard is “ the value of the STATUS parameter may be used in an implementation defined manner by the host simulator“. The problem with using this status code is that what it does depends on the simulator. You would think that the status integer becomes the exit code when called from a Linux shell, but that’s not the case, at least not with ModelSim. There’s the version without any parameters, which is the one I always use, and there’s another that takes a status integer as a constant input. As we can see from the code below, it comes in two overloaded flavors. # Errors: 0, Warnings: VHDL finish procedure is defined in the standard ENV package. # Time: 1 ms Iteration: 0 Instance: /using_finish_tb After the testbench completes, the simulator quits, and at the last line, we are back in the Linux vsim -c -do 'vsim ing_finish_tb run -all' The example below shows a testbench using the finish procedure started in ModelSim batch mode in Linux. If you are using scripts to start the simulation, you want to return control to the calling script after the simulation finishes. By doing so, the finish procedure will behave in the same way as the stop procedure that we will discuss in the next section of this article.Īn advantage of using finish is that you can use the default behavior when simulating in batch mode. Fortunately, we can prevent this behavior by adding the “-onfinish stop” option to the vsim command, as shown below. If you click Yes, ModelSim is going to quit. If you are running ModelSim in the GUI version, a popup will appear saying “Are you sure you want to finish?”. Note that finish quits the simulation by default. Replace this line with your testbench logic The code below ends the simulation when we reach the last line of the testbench sequencer process. You have to import “finish” from the STD.ENV package, and you have to compile the testbench in VHDL-2008 or newer to use it. The VHDL finish procedure is my favorite way of stopping a VHDL testbench that completes without errors.